Semiconductor package having side walls and method for manufacturing the same

ABSTRACT

A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priorities to Korean patent applicationnumbers 10-2008-0021983 filed on Mar. 10, 2008 and 10-2008-0085386 filedon Aug. 29, 2008, which are incorporated herein by reference in theirentireties.

BACKGROUND OF THE INVENTION

The present invention relates generally to a semiconductor package and amethod for manufacturing the same, and more particularly to asemiconductor package having side walls formed around a semiconductorchip to increase the bonding area of the semiconductor chip package.

Semiconductor chips capable of storing large amounts of data andprocessing the data rapidly and semiconductor packages utilizing suchsemiconductor chips have been developed. Chip scale packages that are nomore than about 100% to 105% of the size of semiconductor chips havebeen disclosed in the art.

One such chip scale package is a wafer level package, which includes asemiconductor chip, bonding pads formed on the semiconductor chip,re-distribution lines connected with the bonding pads, and solder ballsplaced on the re-distribution lines. In the wafer level package above,the size of the semiconductor package considerably decreases, becausethe solder balls are placed on the semiconductor chip. The solder ballsare attached to the re-distribution lines and placed on thesemiconductor chip according to the international standard of JointElectron Device Engineering Council (JEDEC).

As semiconductor chip manufacturing processes continue to evolve, thesize of the semiconductor chip gradually decreases. Therefore, problemsassociated with the decrease in the size of the semiconductor chip, inthat it is difficult to attach solder balls on the semiconductor chipaccording to the international standard of JEDEC.

SUMMARY OF THE INVENTION

Embodiments of the present invention include a semiconductor packagewhich provides areas for placing solder balls even when the size of asemiconductor chip decreases.

Also, embodiments of the present invention include a method formanufacturing the semiconductor package.

In one embodiment of the present invention, a wafer level semiconductorpackage comprises a semiconductor chip having an upper surface, sidesurfaces which are connected with the upper surface, and bonding padswhich are placed on the upper surface; a first insulation layer patterncovering the upper surface and the side surfaces and exposing thebonding pads; re-distribution lines placed on the first insulation layerpattern and having first re-distribution line parts which have one endsconnected with the bonding pads and correspond to the upper surface ofthe semiconductor chip and second re-distribution line parts whichextend from the first re-distribution line parts outside the sidesurfaces of the semiconductor chip; and a second insulation layerpattern exposing portions of the first re-distribution line parts andthe second re-distribution line parts.

An upper surface of the first insulation layer pattern is parallel tothe upper surface of the semiconductor chip, and side surfaces of thefirst insulation layer pattern are parallel to the side surfaces of thesemiconductor chip.

The first insulation layer pattern comprises an organic layer patterncontaining organic substance.

The wafer level semiconductor package further comprises connectionmembers electrically connected with the exposed portions of the firstre-distribution line parts and the second re-distribution line parts.

The semiconductor chip further has fuse boxes, which are insulated bythe first insulation layer pattern.

In another embodiment of the present invention, a wafer levelsemiconductor package comprises a semiconductor chip having an uppersurface, side surfaces which are connected with the upper surface, andbonding pads which are placed on the upper surface; a first insulationlayer pattern placed along the side surfaces of the semiconductor chip;re-distribution lines placed on the semiconductor chip and having firstre-distribution line parts which are connected with the bonding pads andsecond re-distribution line parts which extend from the firstre-distribution line parts over the first insulation layer pattern; anda second insulation layer pattern exposing portions of the firstre-distribution line parts and the second re-distribution line parts.

A thickness of the first insulation layer pattern is substantially thesame as that of the semiconductor chip, and an upper surface of thefirst insulation layer pattern is positioned on substantially the sameplane as the upper surface of the semiconductor chip.

The first insulation layer pattern comprises an organic layer patterncontaining organic substance.

The wafer level semiconductor package further comprises connectionmembers electrically connected with the exposed portions of the firstre-distribution line parts and the second re-distribution line parts.

In another embodiment of the present invention, a method formanufacturing a wafer level semiconductor package comprises the steps ofplacing at least two semiconductor chips having bonding pads on acarrier substrate; forming a first insulation layer pattern on thecarrier substrate to cover upper surfaces of the semiconductor chips andside surfaces of the semiconductor chips which are connected with theupper surfaces and to expose the bonding pads; forming re-distributionlines on the first insulation layer pattern, the re-distribution lineshaving first re-distribution line parts which are connected with thebonding pads and second re-distribution line parts which extend from thefirst re-distribution line parts outside the side surfaces of thesemiconductor chips; forming a second insulation layer pattern on thefirst insulation layer pattern to expose portions of the firstre-distribution line parts and the second re-distribution line parts;and individualizing the respective semiconductor chips.

The step of placing the semiconductor chips comprises the steps ofinspecting semiconductor chips formed on a wafer and sorting goodsemiconductor chips and bad semiconductor chips; individualizing thegood and bad semiconductor chips from the wafer; and placing the goodsemiconductor chips on the carrier substrate.

The step of forming the first insulation layer pattern on the carriersubstrate comprises the steps of applying a flowable insulation materialon the carrier substrate and thereby forming a first insulation layer tocover the semiconductor chips; baking the first insulation layer; andpatterning the first insulation layer to define openings for exposingthe bonding pads and to expose a portion of the carrier substratebetween the semiconductor chips.

The step of forming the first insulation layer pattern on the carriersubstrate comprises the steps of applying a flowable insulation materialon the carrier substrate and thereby forming a first insulation layer tocover the semiconductor chips; baking the first insulation layer; andpatterning the first insulation layer to define openings for exposingthe bonding pads.

The method further comprises the step of placing connection members onthe exposed portions of the first re-distribution line parts and thesecond re-distribution line parts.

The connection members comprise solder balls containing solder.

Before the step of individualizing the semiconductor chips, the methodfurther comprises the step of separating the carrier substrate from thesemiconductor chips.

In still another aspect of the present invention, a semiconductorpackage comprises a semiconductor chip having bonding pads; a chipreceiving body having side walls and a bottom plate which is coupledwith the side walls to define a receiving space for receiving thesemiconductor chip; and re-distribution lines having first ends whichare electrically connected with the bonding pads and second ends whichface away from the first ends and extend over upper surfaces of the sidewalls of the chip receiving body.

The semiconductor package further comprises a solder resist patternhaving openings for exposing portions of the re-distribution lines.

The openings expose portions of first re-distribution line parts of there-distribution lines, which correspond to an upper surface of thesemiconductor chip, and portions of second re-distribution line parts ofthe re-distribution lines, which correspond to the upper surfaces of theside walls.

The semiconductor package further comprises connection memberselectrically connected with the exposed portions of the firstre-distribution line parts and the second re-distribution line parts.

Side surfaces of the bottom plate contact inner surfaces of the sidewalls.

The bottom plate and the side walls are made of any one of metal andsynthetic resin.

The semiconductor package further comprises an adhesive memberinterposed between the semiconductor chip and the bottom plate.

The semiconductor package further comprises an insulation layer havingopenings for exposing the bonding pads which are formed on the uppersurface of the semiconductor chip.

A total thickness of the bottom plate, the semiconductor chip and theinsulation layer is the same as a height of the side walls.

At least two semiconductor chips are located on the bottom plate in thereceiving space in the form of a matrix.

At least two semiconductor chips are the same kind of semiconductorchips.

At least two semiconductor chips are different kinds of semiconductorchips.

Bonding pads of at least two semiconductor chips are electricallyconnected with each other by the re-distribution lines.

At least two semiconductor chips are stacked on the bottom plate in thereceiving space and are electrically connected with each other bythrough-electrodes which are electrically connected with re-distributionlines.

The semiconductor chips are the same kind of semiconductor chips.

The semiconductor chips are different kinds of semiconductor chips.

In yet another embodiment of the present invention, a method formanufacturing a semiconductor package comprises the steps of formingpartition walls on a bottom plate in the form of lattices and therebydefining receiving spaces; placing good semiconductor chips havingbonding pads, in the respective receiving spaces; formingre-distribution lines having first ends which are electrically connectedwith the bonding pads and second ends which face away from the firstends and extend over the partition walls; and cutting the partitionwalls and the bottom plate to individualize the semiconductor chips.

After the step of forming the re-distribution lines, the method furthercomprises the step of forming a solder resist pattern to cover thepartition walls and the semiconductor chips and have openings forexposing portions of the re-distribution lines.

The bottom plate has the shape of a disc.

Before the step of forming the partition walls, the method furthercomprises the step of defining through-holes in partition wall formingregions on the bottom plate by a pressing process.

The bottom plate and the partition walls are made of any one of metaland synthetic resin.

The step of placing the good semiconductor chips on the bottom platecomprises the step of forming an adhesive member on at least one of thesemiconductor chips and the bottom plate.

Before the step of forming the re-distribution lines, the method furthercomprises the steps of applying a flowable insulation material on thesemiconductor chips and thereby forming an insulation layer which coversthe semiconductor chips; and patterning the insulation layer and therebyexposing the bonding pads.

In the step of placing the semiconductor chips in the respectivereceiving spaces defined by the partition walls, at least twosemiconductor chips are located on the bottom plate in each receivingspace in the form of a matrix.

The semiconductor chips are the same kind of semiconductor chips ordifferent kinds of semiconductor chips.

In the step of placing the semiconductor chips in the respectivereceiving spaces defined by the partition walls, at least twosemiconductor chips are sequentially stacked on the bottom plate in eachreceiving space and are electrically connected with each other bythrough-electrodes.

The semiconductor chips are the same kind of semiconductor chips ordifferent kinds of semiconductor chips.

In the step of placing the semiconductor chips in the respectivereceiving spaces defined by the partition walls, a semiconductor chipmodule including a plurality of stacked semiconductor chips, which areelectrically connected with one another by through-electrodes, is placedin each receiving space.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a wafer level semiconductor package inaccordance with one embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line I-I′ of FIG. 1.

FIG. 3 is a plan view showing a wafer level semiconductor package inaccordance with another embodiment of the present invention.

FIG. 4 is a cross-sectional view taken along the line II-II′ of FIG. 3.

FIGS. 5 through 7 are cross-sectional views showing a method formanufacturing the wafer level semiconductor package in accordance withone embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a semiconductor package inaccordance with another embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a semiconductor package inaccordance with still another embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a semiconductor package inaccordance with another embodiment of the present invention.

FIGS. 11 through 26 are plan views and cross-sectional views showing amethod for manufacturing the semiconductor package in accordance withanother embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

FIG. 1 is a plan view showing a semiconductor package in accordance withone embodiment of the present invention. FIG. 2 is a cross-sectionalview taken along the line I-I′ of FIG. 1.

Referring to FIGS. 1 and 2, a semiconductor package 100 includes asemiconductor chip 110, a first insulation layer pattern 120,re-distribution lines 130, and a second insulation layer pattern 140. Inaddition, the semiconductor package 100 may further include connectionmembers 150 containing, for example, a solder.

According to an embodiment of the present invention, the semiconductorchip 110 may have the shape of a rectangular hexahedron, although itshould be understood that the semiconductor chip 110 may also have anynumber of other various shapes.

The semiconductor chip 110 having the shape of a rectangular hexahedronincludes an upper surface 111, a lower surface 112 facing away from theupper surface 111, and side surfaces 113 connecting the upper surface111 and the lower surface 112.

The semiconductor chip 110 may further include a circuit section (notshown) and bonding pads 115. In addition, the semiconductor chip 110 mayfurther include fuse boxes 117.

The circuit section (not shown) includes a data storage part for storingdata and a data processing part for processing the data.

The bonding pads 115 are electrically connected with the circuitsection. The bonding pads 115 receive data input to the circuit sectionfrom external devices and output data from the circuit section to theexternal devices. By way of example, signals inputted to the bondingpads may include power supply signals, control signals, address signals,and data signals.

The fuse boxes 117 function to repair the circuit section.

The first insulation layer pattern 120 is formed over the upper surface111 and the side surfaces 113 of the semiconductor chip 110. Forexample, as shown in FIG. 2, an upper surface of the first insulationlayer pattern 120 may include an upper surface, which is parallel to theupper surface 111 of the semiconductor chip 110, and side surfaces,which are parallel to the side surfaces 113 of the semiconductor chip110. The first insulation layer pattern 120 includes first openingscorresponding to the bonding pads 115, which expose the bonding pads115.

The first insulation layer pattern 120 may comprise, an organic layercontaining an organic substance. Alternatively, the first insulationlayer pattern 120 may comprise an inorganic layer containing aninorganic substance.

In the present embodiment, the first insulation layer pattern 120, whichcovers the upper surface 111 and the side surfaces 113 of thesemiconductor chip 110, increases the area for locating the connectionmembers 150 electrically connected with the re-distribution lines 130 aswill be described below. As a result, the size of the semiconductor chip110 can be reduced while allowing the connection members 150 to belocated according to the international standard of JEDEC.

The re-distribution lines 130 are formed on the upper surface of thefirst insulation layer pattern 120. In the present embodiment, eachre-distribution line 130 has a first re-distribution line part 132 and asecond re-distribution line part 134. An end of the firstre-distribution line part 132 is electrically connected with the bondingpad 115, and the second re-distribution line part 134 extends from theopposite end of the first re-distribution line part 132 over the uppersurface of the first insulation layer pattern 120 along an edge thereof,the edge corresponding to the side surface 113 of the semiconductor chip110.

The re-distribution lines 130 may be formed of a conductive material,for example, copper. When the re-distribution lines 130 are formed ofcopper, the re-distribution lines 130 may include metal seed patterns,which have substantially the same shape as the re-distribution lines130.

The second insulation layer pattern 140 is formed over the firstinsulation layer pattern 120. The second insulation layer pattern 140may comprise an organic layer containing an organic substance.Alternatively, the second insulation layer pattern 140 may comprise aninorganic layer containing an inorganic substance.

The second insulation layer pattern 140 includes openings exposingportions of the first re-distribution line parts 132 and portions of thesecond re-distribution line parts 134. In the present embodiment, theopenings are located according to the international standard of JEDEC.

The connection members 150 are electrically connected with the firstre-distribution line parts 132 and the second re-distribution line parts134, which are exposed through the openings defined in the secondinsulation layer pattern 140. The connection members 150 may comprisesolder balls containing solder.

FIG. 3 is a plan view of a semiconductor package in accordance withanother embodiment of the present invention. FIG. 4 is a cross-sectionalview of the semiconductor package of FIG. 3, taken along the line II-II′of FIG. 3.

Referring to FIGS. 3 and 4, a semiconductor package 200 includes asemiconductor chip 210, a first insulation layer pattern 220,re-distribution lines 230, and a second insulation layer pattern 240. Inaddition, the semiconductor package 200 may include connection members250 containing solder.

The semiconductor package 200 according to the present embodiment can beapplied to a semiconductor chip that does not include a fuse box.

The semiconductor chip 210 may have the shape of, for example, arectangular hexahedron, although it should be understood that thesemiconductor chip 210 may have any number of other various shapes.

The semiconductor chip 210 includes an upper surface 211, a lowersurface 212 facing away from the upper surface 211, and side surfaces213 which connect the upper surface 211 and the lower surface 212.

Also, the semiconductor chip 210 may include a circuit section (notshown) and bonding pads 215.

The circuit section includes a data storage part for storing data and adata processing part for processing data.

The bonding pads 215 are electrically connected with the circuitsection. The bonding pads 215 function to input data from externaldevices to the circuit section or output data from the circuit sectionto the external devices. Signals that may be input to the bonding pads215 include, but are not limited to, power supply signals, controlsignals, address signals, and data signals. In the present embodiment,the bonding pads 215 can, for example, be formed on a central portion ofthe upper surface 211 of the semiconductor chip 210.

The first insulation layer pattern 220 is formed along the side surfaces213 of the semiconductor chip 210. The first insulation layer pattern220 formed along the side surfaces 213 of the semiconductor chip 210may, for example, may be formed in the shape of a band. In the presentembodiment, the first insulation layer pattern 220 is not formed on theupper surface 211 of the semiconductor chip 210, but rather only alongthe side surfaces 213 of the semiconductor chip as shown in FIG. 4.

The first insulation layer pattern 220 includes an upper surface whichis, for example, parallel to the upper surface 211 of the semiconductorchip 210. The thickness of the first insulation layer pattern 220 issubstantially the same as that of the semiconductor chip 210.

In the present embodiment, the first insulation layer pattern 220 maycomprise, for example, an organic layer containing an organic substance.Alternatively, the first insulation layer pattern 220 may comprise aninorganic layer containing an inorganic substance. As yet anotheralternative, the first insulation layer pattern 220 may be formed ofinsulating synthetic resin or the like.

In the present embodiment, the first insulation layer pattern 220, whichis formed along the side surfaces 213 and covers the side surfaces 213of the semiconductor chip 210, increases the area available for locatingthe connection members 250 electrically connected with there-distribution lines 230, as will be described below, allowing theconnection members 250 to be located according to the internationalstandard of JEDEC.

The re-distribution lines 230 are placed on the upper surface 211 of thesemiconductor chip 210 and the upper surface of the first insulationlayer pattern 220. In the present embodiment, each re-distribution line230 has a first re-distribution line part 232 and a secondre-distribution line part 234. A first end of the first re-distributionline part 232 is electrically connected with the bonding pad 215, andthe second re-distribution line part 234 extends from the opposite endof the first re-distribution line part 232 over the upper surface of thefirst insulation layer pattern 220, which corresponds to the outside ofthe side surface 213 of the semiconductor chip 210.

The re-distribution lines 230 are formed of a conductive material, forexample, copper. When the re-distribution lines 230 to are formed ofcopper, the re-distribution lines 230 may include metal seed patternshaving substantially the same shape as the re-distribution lines 230.

The second insulation layer pattern 240 is formed over both thesemiconductor chip 210 and the first insulation layer pattern 220. Thesecond insulation layer pattern 240 may comprise an organic layercontaining an organic substance. Alternatively, the second insulationlayer pattern 240 may comprise an inorganic layer containing aninorganic substance.

The second insulation layer pattern 240 includes openings definedtherein which expose portions of the first and second parts 232, 234 ofthe re-distribution lines 230.

The connection members 250 are electrically connected with portions ofthe first re-distribution line parts 232 and portions of the secondre-distribution line parts 234 which are exposed through the openingsdefined in the second insulation layer pattern 240. For example, theconnection members 250 may comprise solder balls containing solder.

FIGS. 5 through 7 are a plan view and cross-sectional views illustratinga method for manufacturing the semiconductor package in accordance withone embodiment of the present invention.

Referring to FIG. 5, in the manufacture a semiconductor package, thestep of locating or placing a plurality of semiconductor chips 110 on acarrier substrate 10 is implemented. In the present embodiment, thecarrier substrate 10 may comprise, for example, a dummy wafer.

The semiconductor chips 110 can include circuit sections (not shown andbonding pads 115, which are electrically connected with the circuitsections. The semiconductor chips 110 may further include fuse boxes117, which are electrically connected with the circuit sections.

In order to locate or place the semiconductor chips 110 on the carriersubstrate 10, a plurality of semiconductor chips, which are formed on awafer (not shown), are inspected through an electric die sorting (EDS)process, such that that it may be determined which semiconductor chipsare good semiconductor chips and which are bad semiconductor chips, thatis, determining which semiconductor chips have sufficiently high qualityfor a given application. Subsequently, the semiconductor chips areindividualized from the wafer through a sawing process. Then, the goodsemiconductor chips are located or placed on the carrier substrate 10using a die pick-up device, etc. At this time, the semiconductor chips110 sorted as having good quality can be located on the carriersubstrate 10 in such a way as to adjoin one another.

Referring to FIG. 6, after locating the semiconductor chips 110 sortedas having good quality on the carrier substrate 10, a first insulationlayer (not shown) is formed on the carrier substrate 10 to cover thesemiconductor chips 110 sorted as having good quality by applying aflowable insulation material on the carrier substrate 10.

According to an embodiment of the present invention, the firstinsulation layer may include a photosensitive substance. However, itshould be understood that the first insulation layer may also be formedof another material. Then, the flowable insulation material covering thecarrier substrate 10 is baked to form the first insulation layer, whichcovers the carrier substrate 10.

The baked first insulation layer is patterned through a patterningprocess that includes a lithographic process and a development process.Through the patterning process, a first insulation layer pattern 120 isformed to have openings 122 that expose the bonding pads 115 of thesemiconductor chips 110 and also expose portions of the carriersubstrate 10 between the semiconductor chips 110.

Alternatively, the baked first insulation layer may be patterned througha patterning process including a lithographic process and a developmentprocess in a manner such that openings 122 for exposing only the bondingpads 115 of the semiconductor chips 110 are defined. That is, the firstinsulation layer pattern 120 is formed on upper surfaces 111 of therespective semiconductor chips 110 and is filled in between thesemiconductor chips 110, by which the first insulation layer pattern 120covers side surfaces 113 of the semiconductor chips 110. In the presentembodiment, the upper surface of the first insulation layer pattern 120becomes parallel to the upper surfaces 111 of the semiconductor chips110.

Referring to FIG. 7, after the first insulation layer is pattern 120 isformed on the carrier substrate 10, re-distribution lines 130 are formedover the carrier substrate 10.

In order to form the re-distribution lines 130, a metal seed layer (notshown) is formed on the first insulation layer pattern 120 and thebonding pads 115 which are exposed through the first insulation layerpattern 120. The metal seed layer can be formed, for example, through asputtering process, and may be formed of a material such as titanium,nickel, vanadium, and copper.

After the metal seed layer is formed on the first insulation layerpattern 120, photoresist patterns (not shown), which have openings forforming the re-distribution lines 130, are formed on the metal seedlayer.

After the photoresist patterns are formed, a plating process isconducted on the metal seed layer which is exposed through the openingsdefined in the photoresist patterns, whereby the re-distribution lines130 are formed. In the present embodiment, each re-distribution line 130includes a first re-distribution line part 132 and a secondre-distribution line part 134. A first end of the first re-distributionline part 132 is electrically connected with the bonding pad 115, andthe second re-distribution line part 134 extends from the opposite endof the first re-distribution line part 132 along a portion of the uppersurface of the first insulation layer pattern 120 which corresponds tothe outside of the side surface 113 of the semiconductor chip 110. There-distribution lines 130 may be formed of a conductive material, forexample, copper.

After the re-distribution lines 130 having first re-distribution lineparts 132 and second re-distribution line parts 134 are formed, a secondinsulation layer pattern 140 is formed on the first insulation layerpattern 120.

The second insulation layer pattern 140 can comprise an organic layercontaining an organic substance. The second insulation layer pattern 140has openings corresponding to the first and second re-distribution lineparts 132, 134 which expose the first re-distribution line parts 132 andthe second re-distribution line parts 134.

Connection members 150 are electrically connected with there-distribution lines 130 which are exposed through the openings definedin the second insulation layer pattern 140. Subsequently, the carriersubstrate 10 is removed from the semiconductor chips 110, and thesemiconductor chips 110 are individualized, and the individualizedsemiconductor chips may then be utilized in the manufacture ofsemiconductor packages.

In the present embodiment, the connection members 150 may be locatedoutside the side surfaces 113 of the semiconductor chips 110. Due tothis fact, the connection members 150 can be formed on the semiconductorchips 110 in accordance with the international standard of JEDEC, evenwhen a semiconductor chip 110 has an area which is smaller than thatprescribed in JEDEC as the international standard for the location ofthe connection members 150. That is, as the reduction of the size ofsemiconductor chips continues, the surface area of the semiconductorchip becomes too small to form connection members in accordance with theinternational standard of JEDEC. However, according to an embodiment ofthe present invention, connection members may be formed in accordancewith the international standard of JEDEC even on such semiconductorchips.

FIG. 8 is a cross-sectional view of a semiconductor package inaccordance with another embodiment of the present invention.

Referring to FIG. 8, a semiconductor package 900 includes asemiconductor chip 600, a chip receiving body 700, and re-distributionlines 800.

The semiconductor chip 600 has the shape of, for example, a rectangularhexahedron although it should be understood that the semiconductor chip600 may also have any number of other various shapes. The semiconductorchip 600 having the shape of a rectangular hexahedron has an uppersurface 610, a lower surface 620 facing away from the upper surface 610,and side surfaces 630 connecting the upper surface 610 and the lowersurface 620.

The semiconductor chip 600 includes a circuit section (not shown) andbonding pads 640.

The circuit section includes a data storage part (not shown) for storingdata and a data processing part (not shown) for processing data.

The bonding pads 640 are located on the upper surface 610 of thesemiconductor chip 600 and are electrically connected with the circuitsection. According to an embodiment of the present invention, thebonding pads 640 may be formed on a central portion of the upper surface610 of the semiconductor chip 600. Alternatively, the bonding pads 640may be located along the edges of the upper surface 610 of thesemiconductor chip 600.

The chip receiving body 700 includes side walls 710 and a bottom plate720. The side walls 710 and the bottom plate 720 of the chip receivingbody 700 define a space for receiving the semiconductor chip 600.

In the present embodiment, the bottom plate 720 has, for example, theshape of a rectangle which is substantially similar to the shape of thesemiconductor chip 600. The side walls 710 are formed on the sidesurfaces of the bottom plate 720. In the present embodiment, the sidesurfaces of the bottom plate 720 contact the inner surfaces of the sidewalls 710, as shown in FIG. 8.

In the present embodiment, the side walls 710 and the bottom plate 720may be made of any one of metal and synthetic resin. By way of example,the bottom plate 720 may comprise a metal, and the side walls 710 maycomprise a synthetic resin. Alternatively, the bottom plate 720 may bemade of synthetic resin, and the side walls 710 may be made of metal. Asyet another alternative, both the side walls 710 and the bottom plate720 may be made of synthetic resin, or both the side walls 710 and thebottom plate 720 may be made of metal.

In the present embodiment, the side walls 710 are made of syntheticresin, and the bottom plate 720 is made of metal. The bottom plate 720comprises a metal which has excellent heat conductivity such as, copper,aluminum, silver, or the like.

In the present embodiment, the semiconductor chip 600 is secured in thechip receiving body 700 including the side walls 710 and the bottomplate 720, by an adhesive member 650 interposed between the bottom plate720 and the lower surface 620 of the semiconductor chip 600. Theadhesive member 650 can comprise, for example, epoxy resin or adouble-sided adhesive tape. It should be understood that other means ofadhesion may also be appropriate for securing the semiconductor chip 600within the chip receiving body 700. The adhesive member 650 may beplaced on the lower surface 620 of the semiconductor chip 600 or theupper surface of the bottom plate 720.

An insulation layer 660 is formed on the upper surface 610 of thesemiconductor chip 600, which is received in the receiving space of thechip receiving body 700. The insulation layer 660 may comprise, forexample, an organic layer. The insulation layer 660 includes openingsexposing the bonding pads 640 formed on the upper surface 610 of thesemiconductor chip 600. In the present embodiment, the insulation layer660 is also formed on the upper surfaces of the side walls 710 when theside walls 710 are made of metal.

In the present embodiment, the total thickness of the bottom plate 720,the adhesive member 650, the semiconductor chip and the insulation layer660 is substantially the same as the height of the side walls 710.

The re-distribution lines 800 have the shape of a line when viewed fromabove. An end of each re-distribution line 800 is electrically connectedwith a corresponding bonding pad 640, which is exposed through theopening of the insulation layer 660, and the opposite end of eachre-distribution line 800 extends onto the upper surface of the side wall710.

In the present embodiment, each re-distribution line includes a firstand a second re-distribution line part 810, 820, the firstre-distribution line part 810 being the portion of a re-distributionline 800 formed on the upper surface 610 of the semiconductor chip 600,and the second first re-distribution line part 820 being the portion ofthe re-distribution line 800 formed on the upper surface of the sidewall 710.

The semiconductor package 900 according to the present embodiment mayfurther include a solder resist pattern 830. The solder resist pattern830 covers the upper surface of the resultant semiconductor chip 600 andthe sidewalls 710 having the re-distribution lines 800 formed thereon.The solder resist pattern 830 includes a plurality of openings whichexpose, for example, portions of the first re-distribution line parts810 and the second re-distribution line parts 820 of the re-distributionlines 800. The openings defined in the solder resist pattern 830 arelocated according to the international standard of JEDEC.

Connection members 835 comprising a low melting point metal, such assolder, are located on the portions of the first re-distribution lineparts 810 and the second re-distribution line parts 820 which areexposed through the openings defined in the solder resist pattern 830.The connection members 835 are located according to the internationalstandard of JEDEC.

FIG. 9 is a cross-sectional view showing a semiconductor package inaccordance with still another embodiment of the present invention.

Referring to FIG. 9, a semiconductor package 900 includes semiconductorchips 662, 664, and 666, a chip receiving body 700, and re-distributionlines 830, 840, and 850.

The chip receiving body 700 includes side walls 710 and a bottom plate720. The side walls 710 and the bottom plate 720 of the chip receivingbody 700 define a space for receiving the semiconductor chips 662, 664,and 666.

In the present embodiment, the bottom plate 720 has the shape of arectangle, although it should be should understood that other the bottomplate 720 may also have any number of other various shapes. The sidewalls 710 are placed on the side surfaces of the bottom plate 720. Inthe present embodiment, the side surfaces of the bottom plate 720contact the inner surfaces of the side walls 710.

In the present embodiment, the side walls 710 and the bottom plate 720may be made of any one of metal and synthetic resin. For example, thebottom plate 720 may be made of metal, and the side walls 710 may bemade of synthetic resin. Alternatively, the bottom plate 720 may be madeof synthetic resin, and the side walls 710 may be made of metal. As yetanother alternative, both the side walls 710 and the bottom plate 720may be made of synthetic resin, or both of the side walls 710 and thebottom plate 720 may be made of metal.

In the present embodiment, the side walls 710 comprise a syntheticresin, and the bottom plate 720 comprises a metal. The bottom plate 720is formed of a metal having excellent heat conductivity such as copper,aluminum, or silver.

In the present embodiment, in order to secure the semiconductor chips662, 664, and 666 in the chip receiving body 700, an adhesive member 650is interposed between the bottom plate 720 and the semiconductor chips662, 664, and 666. By way of example, the adhesive member 650 maycomprise epoxy resin or a double-sided adhesive tape. The adhesivemember 650 may be placed on the lower surfaces of the semiconductorchips 662, 664 and 666 or alternatively the adhesive member 650 may beplaced on the upper surface of the bottom plate 720.

The plurality of semiconductor chips 662, 664, and 666 are located onthe bottom plate 720 of the chip receiving body 700. The plurality ofsemiconductor chips 662, 664, and 666 may be located on the bottom plate720 in the form of a matrix. For example, the semiconductor chips 662,664, and 666 may be located on the bottom plate 720 in the form of a 3×1matrix, a 3×2 matrix, a 3×3 matrix, etc. In the present embodiment, thesemiconductor chips 662, 664, and 666 are located in the form of a 3×1matrix.

Hereinbelow, the middle semiconductor chip among the semiconductor chips662, 664, and 666 located on the bottom plate 720, is defined as a firstsemiconductor chip 662, and the semiconductor chips, which are locatedon the sides of the first semiconductor chip 662 are defined as a secondsemiconductor chip 664 and a third semiconductor chip 666 respectively.The first semiconductor chip 662 has first bonding pads 663, the secondsemiconductor chip 664 has second bonding pads 665, and the thirdsemiconductor chip 666 has third bonding pads 667.

In the present embodiment, the first through third semiconductor chips662, 664, and 666 may be the same kind of semiconductor chips, oralternatively at least one of the first through third semiconductorchips 662, 664, and 666 may be a different kind of semiconductor chip.For example, the first semiconductor chip 662 may be a systemsemiconductor chip, and the second and third semiconductor chips 664 and666 may be memory semiconductor chips.

Hereinbelow, first re-distribution lines 830 are electrically connectedwith the first bonding pads 663, second re-distribution lines 840 areelectrically connected with the second bonding pads 665, and thirdre-distribution lines 850 are electrically connected with the thirdbonding pads 667.

The first re-distribution lines 830 extend to the upper surfaces of thesecond and third semiconductor chips 664 and 666, and the second andthird re-distribution lines 840 and 850 extend to the upper surfaces ofthe side walls 710 of the chip receiving body 700.

A solder resist pattern 835 is formed on first through thirdre-distribution lines 830, 840, and 850. Openings are defined in thesolder resist pattern 835 which expose portions of the first throughthird re-distribution lines 830, 840, and 850.

Connection members 855 are formed on the portions of the first throughthird re-distribution lines 830, 840, and 850 which are exposed throughthe openings defined in the solder resist pattern 835. The connectionmembers 855 contain a low melting point metal such as solder.

FIG. 10 is a cross-sectional view showing a semiconductor package inaccordance with another embodiment of the present invention.

Referring to FIG. 10, a semiconductor package 900 includes semiconductorchips 672, 674, and 676, a chip receiving body 700, and re-distributionlines 860, 870, and 880. The semiconductor package 900 may furtherinclude a solder resist pattern 830 and connection members 885.

The chip receiving body 700 includes side walls 710 and a bottom plate720.

The side walls 710 and the bottom plate 720 of the chip receiving body700 define a space for receiving the semiconductor chips 672, 674 and676.

In the present embodiment, the bottom plate 720 has, for example, theshape of a rectangle, although it should be understood that the bottomplate may alternatively have another shape. The side walls 710 areplaced on the side surfaces of the bottom plate 720. In the presentembodiment, the side surfaces of the bottom plate 720 contact, forexample, the inner surfaces of the side walls 710.

In the present embodiment, the side walls 710 and the bottom plate 720may be made of any one of metal and synthetic resin. For example, thebottom plate 720 may be made of metal, and the side walls 710 may bemade of synthetic resin. Alternatively, the bottom plate 720 may be madeof synthetic resin, and the side walls 710 may be made of metal. As yetanother alternative, both the side walls 710 and the bottom plate 720may be made of synthetic resin, or both the side walls 710 and thebottom plate 720 may be made of metal.

In the present embodiment, the side walls 710 and the bottom plate 720are made of metal. The bottom plate 720 is formed of a material whichhas excellent heat conductivity, for example copper, aluminum, orsilver.

In the present embodiment, in order to secure the semiconductor chip 672in the chip receiving body 700 including the side walls 710 and thebottom plate 720, an adhesive member 650 is interposed between thebottom plate 720 and the semiconductor chip 672. The adhesive member 650may comprise, for example, epoxy resin or a double-sided adhesive tape.The adhesive member 650 may be placed on the lower surface of thesemiconductor chip 672 or the upper surface of the bottom plate 720.

The plurality of semiconductor chips 672, 674, and 676 are sequentiallystacked on the bottom plate 720 of the chip receiving body 700.Hereinbelow, the semiconductor chips, which are stacked on the bottomplate 720, are respectively defined as first through third semiconductorchips 672, 674, and 676.

The first semiconductor chip 672 is placed on the adhesive member 650,the second semiconductor chip 674, is placed on the first semiconductorchip 672, and the third semiconductor chip 676 is placed on the secondsemiconductor chip 674.

The first semiconductor chip 672 has first bonding pads 673, the secondsemiconductor chip 674 has second bonding pads 675, and the thirdsemiconductor chip 676 has third bonding pads 677.

The first semiconductor chip 672 has first through-electrodes 672 a, thesecond semiconductor chip 674 has second through-electrodes 674 a, andthe third semiconductor chips 676 has third through-electrodes 676 a. Inthe present embodiment, the first through third through-electrodes 672a, 674 a, and 676 a are located at substantially the same position, suchthat the first through third through electrodes 672 a, 674 a, and 676 aare aligned in the vertical direction.

In the present embodiment, the first through third semiconductor chips672, 674, and 676 may be the same kind of semiconductor chips.Alternatively, at least one of the first through third semiconductorchips 672, 674, and 676 may be a different kind of semiconductor chip.For example, the first semiconductor chip 672 may be a systemsemiconductor chip, and the second and third semiconductor chips 674 and676 may be memory semiconductor chips.

Hereinbelow, first re-distribution lines 860 are electrically connectedwith both the first bonding pads 673 and the first through-electrodes672 a, second re-distribution lines 870 are electrically connected withboth the second bonding pads 675 and the second through-electrodes 674a, and third re-distribution lines 880 are electrically connected withboth the third bonding pads 677 and the third through-electrodes 676 a.

According to the present embodiment, the first re-distribution lines 860are electrically connected with the second through-electrodes 674 a, andthe second re-distribution lines 870 are electrically connected with thethird through-electrodes 676 a. Further, the third re-distribution lines880 are formed to extend over the upper surfaces of the side walls 710of the chip receiving body 700.

The solder resist pattern 830 is formed to cover the thirdre-distribution lines 880 which extend over the upper surfaces of theside walls 710. Openings are defined in the solder resist pattern 830which expose portions of the third re-distribution lines 880.

Connection members 855 are electrically connected with the portions ofthe third re-distribution lines 880 which are exposed through theopenings defined in the solder resist pattern 830. The connectionmembers 855 are formed of a low melting point metal, for example solder.

The operation of semiconductor chips results in the generation of heat.For example, as the data processing speed of semiconductor chips in asemiconductor package increases, the amount of heat generated may besuch that the semiconductor package fails to operate properly. In thepresent embodiment, a large amount of heat generated in thesemiconductor chips stacked upon one another can be dissipated to theoutside through the side walls 710 and the bottom plate 720 of the chipreceiving body 700, such that the data processing speed of thesemiconductor package 900 can be increased.

FIGS. 11 through 26 are plan views and cross-sectional views showing amethod for manufacturing the semiconductor package in accordance withanother embodiment of the present invention.

FIG. 11 is a plan view showing a bottom plate used for manufacturingsemiconductor packages according to the present invention. FIG. 12 is across-sectional view taken along the line III-III′ of FIG. 11.

Referring to FIGS. 11 and 12, in order to manufacture semiconductorpackages, a bottom plate 701 is prepared. In the present embodiment, thebottom plate 701 has the shape of a disc when viewed from above. Forexample, the bottom plate 701 has the same shape as a wafer, or acircular disc. In the present embodiment, the bottom plate 701 isformed, for example, of a metal having excellent heat conductivity, suchas aluminum, aluminum alloy, copper, or copper alloy. Alternatively, thebottom plate 701 may be formed of a synthetic resin.

FIG. 13 is a plan view showing the defining of through-holes in thebottom plate shown in FIG. 11. FIG. 14 is a sectional view taken alongthe line IV-IV′ of FIG. 13.

Referring to FIGS. 13 and 14, through-holes 703 are defined at regions702 of the bottom plate 701 where partition walls are to be formed aswill be described later, such that the through-holes 703 adjoin oneanother. The regions 702 are defined in the form of lattices on thebottom plate 701. The through-holes 703 adjoining one another can bedefined in the bottom plate 701, for example, by conducting a pressingprocess in the regions 702. The through-holes 703 have the shape ofslots when viewed from above.

FIG. 15 is a plan view showing the formation of partition walls on thebottom plate shown in FIG. 13. FIG. 16 is a to cross-sectional viewtaken along the line V-V′ of FIG. 15.

Referring to FIGS. 15 and 16, after the through-holes 703 are defined inthe bottom plate 701 as shown in FIG. 13, partition walls 715 are formedalong the regions 702 shown in FIG. 13. Receiving spaces are defined onthe bottom plate 701 by the partition walls 715 which are formed to havea predetermined height when measured from the upper surface of thebottom plate 701. In the present embodiment, the partition walls 715 maybe formed by a process including, for example, pouring synthetic resinin molds. The partition walls 715 may be arranged in a lattice patternwhen viewed from the top. The partition walls 715 pass through thebottom plate 701 due to the presence of the through-holes 703.Therefore, the side surfaces of the partition walls 715 contact the sidesurfaces of the bottom plate 701. Alternatively, the partition walls 715may be formed by arranging metal plates, each having the shape of arectangular hexahedron, into a lattice pattern within the through-holes703.

A plurality of chip mounting regions 704 are defined on the bottom plate701, by the partition walls 715 having the lattice pattern.

FIG. 17 is a plan view showing the formation of the adhesive members inthe chip mounting regions shown in FIG. 15. FIG. 18 is a cross-sectionalview taken along the line VI-VI′ of FIG. 17.

Referring to FIGS. 17 and 18, after the partition walls 715 are formedon the bottom plate 701, adhesive members 650 are placed in therespective chip mounting regions 704, which are defined by the partitionwalls 715 on the bottom plate 701. The adhesive members 650 may comprisean adhesive tape or a flowable adhesive containing epoxy. Alternatively,the adhesive members 650, may be placed on the lower surfaces ofsemiconductor chips, which are subsequently placed in the respectivechip mounting regions 704.

FIG. 19 is a plan view showing the locating of the semiconductor chipsin the chip mounting regions shown in FIG. 18. FIG. 20 is across-sectional view taken along the line VII-VII′ of FIG. 19.

Referring to FIGS. 19 and 20, semiconductor chips 600 are located in therespective chip mounting regions 704 defined by the partition walls 715and positioned on the bottom plate 701. Each semiconductor chip 600 hasan upper surface 610, a lower surface 620 which faces away from theupper surface 610, and side surfaces 630 which connect the upper surface610 and the lower surface 620. Each semiconductor chip 600 has the shapeof, for example, a rectangular hexahedron, although it should beunderstood that a semiconductor chip may have any number of other shapesas well.

Bonding pads 640 are placed on the upper surface 610 of eachsemiconductor chip 600. By way of example, the bonding pads 640 may beplaced on a central portion of the upper surface 610 of thesemiconductor chip 600.

The lower surface 620 of each semiconductor chip 600 is placed on thebottom plate 701 and is bonded thereto by an adhesive member 650. In thepresent embodiment, the partition walls 715 extend above the uppersurfaces 610 of the semiconductor chips 600 by a predetermined amount.

FIG. 21 is a plan view showing the formation of an insulation layer onthe upper surfaces of the semiconductor chips shown in FIG. 19. FIG. 22is a sectional view taken along the line VIII-VIII′ of FIG. 21.

Referring to FIGS. 21 and 22, after the respective semiconductor chips600 are attached to the adhesive members 650, an insulation material 650is applied on the semiconductor chips 600, by which an insulation layer660 for covering the upper surfaces 610 of the semiconductor chips 600is formed.

In order to form the insulation layer 660, a flowable insulationmaterial 665 is applied on the upper surfaces 610 of the semiconductorchips 600. Then the flowable insulation material 665 is uniformly spreadby a scraper 667, so as to form an insulation layer 660 on the uppersurfaces 610 of the semiconductor chips 600. In the present embodiment,the total thickness of the bottom plate 701, the adhesive member 650,the semiconductor chip 600 and the insulation layer 660 aresubstantially the same as the height of the partition wall 715. As analternative, in the present embodiment, the insulation layer 660 may beformed on the partition walls 715 in addition to the semiconductor chips600.

FIG. 23 is a plan view showing the patterning of the is insulation layershown in FIG. 21. FIG. 24 is a cross-sectional view taken along the lineIX-IX′ of FIG. 23.

Referring to FIGS. 23 and 24, openings exposing the bonding pads 640 aredefined by patterning the insulation layer 660 formed on thesemiconductor chips 600.

FIG. 25 is a cross-sectional view showing re-distribution lines, asolder resist pattern, and connection members, which are formed on thesemiconductor chips shown in FIG. 24.

Referring to FIG. 25, re-distribution lines 800 are formed on thesemiconductor chips 600 and the partition walls 715. In the presentembodiment, an end of each re-distribution line 800 is electricallyconnected with a corresponding bonding pad 640 of the semiconductor chip600, and the opposite end of each re-distribution line 800 extendspartially or entirely over the upper surface of the partition wall 715.

A solder resist pattern 830 covers the upper surfaces 610 of thesemiconductor chips 600 and the upper surfaces of the partition walls715. Openings are defined by patterning the solder resist pattern 830.The openings expose first re-distribution line parts of there-distribution lines 800, which correspond to the upper surfaces 610 ofthe semiconductor chips 600, and second re-distribution line parts ofthe re-distribution lines 800, which correspond to the upper surfaces ofthe partition walls 715.

After the solder resist pattern 830 is patterned and the openings aredefined, connection members 835 are connected to portions of the firstand second re-distribution line parts of the re-distribution lines 800,which are exposed through the openings defined in the solder resistpattern 830.

FIG. 26 is a cross-sectional view showing a semiconductor packagesformed by cutting the partition walls shown in FIG. 25.

Referring to FIG. 26, after the connection members 835 are placed on there-distribution lines 800 of the semiconductor chips 600, the partitionwalls 715 are cut, such that, semiconductor packages 900 each havingside walls 710 and a bottom plate 720 are manufactured.

Although it was described in the method for manufacturing asemiconductor package according to the present embodiment that eachsemiconductor chip 600 is placed in a chip mounting region 704 definedby the partition walls 715, it should be readily understood that aplurality of semiconductor chips 662, 664, and 666 can be placed in achip mounting region in the form of a matrix as shown in FIG. 9.

When the plurality of semiconductor chips 662, 664, and 666 are placedin each chip mounting region in the form of a matrix, the semiconductorchips 662, 664, and 666 may each be the same kind of semiconductorchips, or alternatively, the semiconductor chips 662, 664, and 666 maybe different kinds of semiconductor chips.

Also, while it was described in the method for manufacturing asemiconductor package according to the present embodiment that eachsemiconductor chip 600 is placed in a chip mounting region 704 definedby the partition walls 715, it should be readily understood that aplurality of semiconductor chips 672, 674, and 676 may be stacked in achip mounting region and be connected with one another bythrough-electrodes 672 a, 674 a, and 676 a as shown in FIG. 10. When theplurality of semiconductor chips 672, 674, and 676 are stacked in a chipmounting region, the individual semiconductor chips may be sequentiallystacked upon one another in the chip mounting region or a semiconductorchip module including a plurality of stacked semiconductor chips may beplaced in the chip mounting region.

When the plurality of semiconductor chips 672, 674, and 676 are stackedin a chip mounting region, the semiconductor chips 672, 674, and 676 maybe the same kind of semiconductor chips, or alternatively, thesemiconductor chips 672, 674, and 676 may be different kinds ofsemiconductor chips.

As is apparent from the above description, in the present invention, asthe size of semiconductor chips and semiconductor chip packagesdecreases, forming connection members according to the internationalstandard of JEDEC becomes increasingly more difficult. According to thepresent invention, the connection members can be located according tothe international standard of JEDEC by forming side walls which coverthe side surfaces of the semiconductor chip. Also, according to thepresent invention the operational characteristics of the semiconductorchip can be improved, because by placing a bottom plate having excellentheat conductivity on the lower surface of the semiconductor chip, heatgenerated in the semiconductor chip can be rapidly dissipated to theoutside.

Moreover, in the present invention, not only it is possible to satisfythe standard ball layout prescribed in JEDEC, but the number of theconnection members in a semiconductor package, which are needed toprocess data with a high density at a high speed, can be increased.

Although specific embodiments of the present invention have beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions, and substitutions arepossible, without departing from the scope and the spirit of theinvention as disclosed in the accompanying claims.

1. A method for manufacturing a wafer level semiconductor package,comprising the steps of: placing at least two semiconductor chips havingbonding pads on a carrier substrate; forming a first insulation layerpattern on the carrier substrate to cover upper surfaces of thesemiconductor chips and side surfaces of the semiconductor chips toexpose the bonding pads, wherein the side surfaces of a semiconductorchips are connected with the upper surface of the semiconductor chip;forming re-distribution lines on the first insulation layer pattern, there-distribution lines comprising: first re-distribution line partsconnected to corresponding bonding pads; and second re-distribution lineparts extending from the first re-distribution line parts beyond theside surfaces of the semiconductor chips; forming a second insulationlayer pattern on predetermined portions of the first insulation layerpattern such that portions of the first re-distribution line parts andthe second re-distribution line parts are exposed; and individualizingthe respective semiconductor chips.
 2. The method according to claim 1,wherein the step of placing the semiconductor chips comprises the stepsof: inspecting semiconductor chips formed on a wafer and determininggood semiconductor chips and bad semiconductor chips; individualizingthe good and bad semiconductor chips from the wafer; and placing thegood semiconductor chips on the carrier substrate.
 3. The methodaccording to claim 1, wherein the step of forming the first insulationlayer pattern on the carrier substrate comprises the steps of: applyinga flowable insulation material on the carrier substrate and so as toform a first insulation layer covering the semiconductor chips; bakingthe first insulation layer; and patterning the first insulation layer todefine openings for exposing the bonding pads and to expose a portion ofthe carrier substrate between adjacent semiconductor chips.
 4. Themethod according to claim 1, wherein the step of forming the firstinsulation layer pattern on the carrier substrate comprises the stepsof: applying a flowable insulation material on the carrier substrate andso as to form a first insulation layer covering the semiconductor chips;baking the first insulation layer; and patterning the first insulationlayer to define openings for exposing the bonding pads.
 5. The methodaccording to claim 1, further comprising the step of: placing connectionmembers on the exposed portions of the first re-distribution line partsand the second re-distribution line parts.
 6. The method according toclaim 1, wherein, before the step of individualizing the semiconductorchips, the method further comprises the step of: separating the carriersubstrate from the semiconductor chips.
 7. A method for manufacturing asemiconductor package, comprising the steps of: forming partition wallson a bottom plate in a lattice pattern so as to define receiving spaces;placing good semiconductor chips having bonding pads, in the respectivereceiving spaces; forming re-distribution lines having first ends whichare electrically connected with the bonding pads and second ends whichface away from the first ends and extend over the partition walls; andcutting the partition walls and the bottom plate to individualize thesemiconductor chips.
 8. The method according to claim 7, wherein, afterthe step of forming the re-distribution lines, the method furthercomprises the step of: to forming a solder resist pattern to cover thepartition walls and the semiconductor chips, the solder resist patternhaving openings for exposing portions of the re-distribution lines. 9.The method according to claim 7, wherein, before the step of forming thepartition walls, the method further comprises the step of: definingthrough-holes in partition wall forming regions on the bottom plate by apressing process.
 10. The method according to claim 7, wherein thebottom plate is made of any one of a metal and synthetic resin and thepartition walls are made of any one of a metal and a synthetic resin.11. The method according to claim 7, wherein, before the step of formingthe re-distribution lines, the method further comprises the steps of:applying an insulation material on the semiconductor chips so as to forman insulation layer for covering the semiconductor chips; and patterningthe insulation layer to expose the bonding pads.
 12. The methodaccording to claim 7, wherein, in the step of placing the semiconductorchips in the respective receiving spaces defined by the partition walls,two or more semiconductor chips are arranged on the bottom plate in eachrespective receiving space in the form of a matrix.
 13. The methodaccording to claim 7, wherein, in the step of placing the semiconductorchips in the respective receiving spaces defined by the partition walls,two or more semiconductor chips are sequentially stacked on the bottomplate in each respective receiving space and the two or moresemiconductor chips are electrically connected with each other bythrough-electrodes.
 14. The method according to claim 7, wherein, in thestep of placing the semiconductor chips in the respective receivingspaces defined by the partition walls, a semiconductor chip moduleincluding a plurality of stacked semiconductor chips, which areelectrically connected with one another by through-electrodes, is placedin each respective receiving space.